Macromodels for IC's are key components of system level simulation. Accuracy and depth of the macro models will determine the confidence level of the system design. We have experience in developing accurate Verilog-A/AMS behavioural models to replicate system level functionality.
Starting with a datasheet we can create the macromodel which includes supply and temperature variations.

Deliverables are:

• Spice model
• Verilog A/AMS models
• Verilog/VHDL for digital logic blocks
• Ocean scripts
• Test benches - Spice, Verilog, System-Verilog, C
• Simulation Report