PDK Development Flow:

 

• Experience in developing PDKs in both BCD and CMOS processes
  • MOS transistors, Resistors, Capacitors, BJTs, Diode, Guard rings, Space fillers, Metal Slotting
  • Advanced features like
    • Abutment
    • Inter-digitated Resistors/MOS
    • Row stacking
    • Stretch handles
  • Macros like
    • Common Centroid structures - BJT/MOS
    • Series/parallel Resistors
    • Schematic Pcells
• Expertise in the use of Skill/Python language in developing
  • PCELLS - Layout and Schematic
  • PyCells - Layout and Schematic for interoperable PDK
  • Utilities within Cadence environment
  • Automating executables
• Knowledge using languagesnthat aide in easy porting of PDKs in open access environment
  • Experience using Python in generating PDK toolkits that are compatible with all open access vendors
  • So one set of PDKs can be ported across all open access EDA softwares
    • Cadence
    • Magma
    • Mentor Graphics
    • Synopsys
• Knowledge of Cadence PDK automation (PAS) software
  • Experience using PAS toolkit in developing PCELLs, technology files, symbols, CDFs

 

PCELLS

     

Examples of pcells developed:

                                                   Stretch Handles in MOS transistors                                Capacitor pcell with Fingers

 

MOS transistor with Row Stacking & Interdigitation:

User can select The number of Rows, Fingers, Multiplier Metal layer to pickup source/drain Contact density and Distribution Dummies Terminal sharing style - Drain-Drain Drain-Source Source-Source Body taps and their spacing

 

MOS Interdigitaion and Schematic pcells:

Schematic Pcell - Parametric equivalent of layout. The symbol creates a schematic based on parameters user selects. A parameterised schematic.

 

MOS Abutment:

                                                           Before Abutment - Two MOS cells                            After Abutment - Diffusion merged

 

Interdigitated Resistors, Matching:

Single row - series matched

Series Matched Resistor Pair - Multiple Rows, with dummies

Parallel Matched Resistor Pair - Multiple Rows with Dummies

 

Pcell generation through Cadence PAS toolkit:

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• Expertise in Assura, Calibre, Dracula, and Diva
  
• Developed verification decks - DRC, LVS, and RCX decks in both BiCMOS and CMOS technologies
• Features of the decks implemented
  • Few thousands of lines long - very elaborate & detailed
  • Multiple voltage tubs
  • Tens of devices in each technology
  • Modular - assists quick addition of layers/devices
• Comprehensive QA methodology - error cells
• Experience supporting, customizing of verification decks from foundries
  • Supported TSMC, AMS, Dongbu PDKs/Verification decks for customers
• Experience with Cadence graphical technology editor in developing verification decks

 

Verification decks using Graphical Technology Editor - GTE:

A lot of times Design houses either are short staffed or lack resources to develop the infrastructure to facilitate more efficient design and layout effort. We have resources and experience in assisting development, support and maintenance of clients CAD infrastructure.

Some of the efforts have been

• Development of Utilities within design environment
• Split model development, Corner toolset
• Ocean scripting
• Maintenance of PDKs, updates and support

• Developed and qualified Symbol, Schematic, Layout, Verilog/VHDL views
• Implemented Place and Route technology files based on technology constraints
• Propose operating boundaries for the library and Develop timing library across PVT corners
• Validate the timing models
  • Extract data from silicon and validate timing libraries
• Support and maintenance
• Toolset Knowledge
  • Cadence library characteriser
  • Synopsys library compiler

We have worked on technologies ranging from 0.18um to 2um. The following table gives a breakdown PDKs delivered.